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UTC LM1851
LINEAR INTEGRATED CIRCUIT
GROUND FAULT INTERRUPTER
DESCRIPTION
The UTC LM1851 is designed to provide ground fault protection for AC power outlets in consumer and industrial environments. Ground fault currents greater than a presentable threshold value will trigger an external SCR-driven circuit breaker to interrupt the AC line and remove the fault condition. In addition to detection of conventional hot wire to ground faults, the neutral fault condition is also detected. Full advantage of the U.S. UL943 timing specification is taken to insure maximum immunity to false triggering due to line noise. Special features include circuitry that rapidly resets the timing capacitor in the event that noise pulses introduce unwanted charging currents and a memory circuit that allows firing of even a sluggish breaker on either half-cycle of the line voltage when external full-wave rectification is used.
DIP-8
SOP-8
FEATURES
* Internal power supply shunt regulator * Externally programmable fault current threshold * Externally programmable fault current integration time * Direct interface to SCR * Operates under line reversal; both load vs line and hot vs neutral * Detects neutral line faults
PIN CONFIGURATION
SCR Trigger INVERTING INPUT NON-INVERTING INPUT GND
1 2 3 4
8 7 6 5
Vcc TIMING CAPACITOR SENSE ITIVITY SET RESISTOR
SENSE AMPLIFIER OUTPUT
UTC
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6
3
2
5
8
D3 Q32 Q15 R10 5k Q35 Q36 R1 D2 100k
UTC
R13 110 R8 390 R9 50k Q12 D5 R5 10k D1 R17 100k Q14 Q13 D6 D16 Q1 D7 Q6 Q24 D8 D18 R4 6k Q3 Q20 C1 D12 Q9 Q21 D11 Q5 Q10 R14 1.2k R15 2k C2 R7 50k Q8 Q11 D20 Q16 R12 Q30 12k Q31 Q34 R6 320 Q22 Q23 D19 Q4 R11 5k Q33 D9 1 Q7 D17 Q2 R2 40k D10 4 Q27 Q18 Q28 D14 D23 Q19 7 D13
Q29
UTC LM1851
D4
INTERNAL SCHEMATIC DIAGRAM
R3 12k
Q25
R16 20k
UNISONIC TECHNOLOGIES CO., LTD.
D22 Q26 Q17
LINEAR INTEGRATED CIRCUIT
D21
2
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UTC LM1851
BLOCK DIAGRAM
Vcc 8
LINEAR INTEGRATED CIRCUIT
TIMING CAPACITOR 7 SENSITIVITY SET RESISTOR 6 SENSE AMPLIFIER OUTPUT 5
D3 Q3
I2 LATCH Q1
Q2 If
I1=
ITH FOR If > 0 3ITH FOR If = 0
D1 If 1 SCR TRIGGER 2 INVERTING INPUT A1 +
Vs Q4 D2
Q5
10V +3 NON-INVERTING INPUT 4 GND
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Current Power Dissipation (Note 1) Operating Temperature Storage Temperature Lead Soldering Temperature DIP-8 (10 sec.) SOP-8 Vapor Phase (60 sec.) Infrared (15 sec.)
SYMBOL
Icc PD Topr Tstg
RATINGS
19 1250 -40 ~ +70 -55 ~ +150 260
UNIT mA
mW C C C C C
TLED 215 220
DC ELECTRICAL CHARACTERISTICS (Ta = 25 C, Iss=5mA)
PARAMETER
Power Supply Shunt Regulator Voltage Latch Trigger Voltage Sensitivity Set Voltage Output Drive Current Output Saturation Voltage Output Saturation Resistance Output External Current Sinking Capability Noise Integration Sink Current Ratio
TEST CONDITIONS
Pin 8, Average Value Pin 7 Pin 8 to Pin 6 Pin 1, With Fault Pin 1, Without Fault Pin 1, Without Fault Pin 1, Without Fault Vpin 1 Held to 0.3V (Note 4) Pin 7, Ratio of Discharge Currents Between No Fault and Fault Conditions
MIN
22 15 6 0.5
TYP
26 17.5 7 1 100 100 5 2.8
MAX
30 20 8.2 2.4 240
UNIT
V V V mA mV mA
2.0 2.0
3.6
A/A
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PARAMETER
Normal Fault Current Sensitivity
LINEAR INTEGRATED CIRCUIT
TEST CONDITIONS MIN TYP MAX UNIT
AC ELECTRICAL CHARACTERISTICS (Ta = 25 C, Iss=5mA)
Figure 1 (Note 3) 3 5 7 mA 500 Fault, Figure 2 (Note 2) Normal Fault Trip Time 18 ms Normal Fault with Grounded Neutral 500 Normal Fault, 2 Neutral, 18 ms Fault Trip Time Figure 2 (Note 2) Note 1: For operation in ambient temperatures above 25, the device must be debated based on a 125 maximum junction temperature and a thermal resistance of 80/W junction to ambient for the DIP and 162/W for the SO Package. Note 2: Average of 10 trials. Note 3: Required UL sensitivity tolerance is such that external trimming of UTC LM1851 sensitivity will be necessary. Note 4: This externally applied current is in addition to the internal ''output drive current '' source.
7
TIMING CAP
-IN +IN RSET GND
2 3
100k
0.047F
1 SCR TRIGGER 5 A Ct 0.002 Iss 8 OP AMP OUTPUT Vcc 1.5M
800Hz 6 4
+ - 300mV
1k
31V
FIGURE 1.Normal Fault Sensitivity Test Circuit
CIRCUIT DESCRIPTION (Refer to Block and Connection Diagram)
The UTC LM1851 operates from 26V as set by an internal shunt regulator, D3. In the absence of a fault (If=0) the feedback path status signal (VS) is correspondingly zero. Under these conditions the capacitor discharge current, I1, sits quiescently at three times its threshold value, ITH, so that noise induced charge on the timing capacitor will be rapidly removed. When a fault current, If, is induced in the secondary of the external sense transformer, the operational amplifier, A1, uses feedback to force a virtual ground at the input as it extracts If. The presence of If during either half-cycle will cause VS to go high, which in turn changes I1 from 3ITH to ITH. Although ITH discharges the timing capacitor during both half-cycles of the line, If only charges the capacitor during the half-cycle in which If exits pin 2. Thus during one half-cycle If-ITH charges the timing capacitor, while during the other half-cycle ITH discharges it. When the capacitor voltage reaches 17.5V, the latch engages and turns off Q3 permitting I2 to drive the gate of an SCR.
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UTC LM1851
APPLICATION CIRCUITS
LINEAR INTEGRATED CIRCUIT
A typical ground fault interrupter circuit is shown in Figure 2. It is designed to operate on 120 VAC line voltage with 5 mA normal fault sensitivity. A full-wave rectifier bridge and a 15k/2W resistor are used to supply the DC power required by the IC. A 1F capacitor at pin 8 used to filter the ripple of the supply voltage and is also connected across the SCR to allow firing of the SCR on either half-cycle. When a fault causes the SCR to trigger, the circuit breaker is energized and line voltage is removed from the load. At this time no fault current flows and the IC discharge current increases from ITH to 3ITH ( see Circuit Description and Block Diagram ). This quickly resets both the timing capacitor and the output latch. At this time the circuit breaker can be reset and the line voltage again supplied to the load, assuming the fault has been removed. A 1000:1 sense transformer is used to detect the normal fault. The fault current, which is basically the difference current between the hot and neutral lines, is stepped down by 1000 and fed into the input pins of the operational amplifier through a 10F capacitor. The 0.0033F capacitor between pin 2 and pin 3 and the 200 pF between pins 3 and 4 are added to obtain better noise immunity. The normal fault sensitivity is determined by the timing capacitor discharging current, ITH. ITH can be calculated by:
ITH=
(1) At the decision point, the average fault current just equals the threshold current, ITH.
7V /2 RSET
ITH=
(2) Where If(rms) is the rms input fault current to the operational amp and the factor of 2 is due to the fact that If charges the timing capacitor only during one half-cycle, while ITH discharges the capacitor continuously. The factor 0.91 converts the rms value to an average value. Combining equations (1) and (2) we have
If (rms) x 0.91 2
RSET=
(3) For example, to obtain 5mA (rms) sensitivity for the circuit in Figure 2 we have:
7V If (rms) x 0.91
RSET=
(4) The correct value for RSET can also be determined from the characteristic curve that plots equation (3). Note that this is an approximate calculation; the exact value of RSET depends on the specific sense transformer used and UTC LM1851 tolerances. Inasmuch as UL943 specifies a sensitivity '' window '' of 4mA ~ 6mA, provision should be made to adjust RSET on a per-product basis. Independent of setting sensitivity, the desired integration time can be obtained through proper selection of the timing capacitor, Ct. Due to the large number of variables involved, proper selection of Ct is best done empirically. The following design example, then should only be used as a guideline. Assume the goal is to meet UL943 timing requirements. Also assume that worst-case timing occurs during GF1 Start-up (S1 closure) with both a heavy normal fault and a 2 grounded neutral fault present. This situation is shown diagrammatically below.
7V 5mA x 0.91 1000
=1.5M
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UTC LM1851
S1
LINEAR INTEGRATED CIRCUIT
HOT HOT
LINE NEUTRAL
GFI NEUTRAL (0.8) I RN 0.4 RB 500
RG 1.6
(0.2) I
I
UL943 specifies 25 ms average trip time under these conditions. Calculation of Ct based upon charging currents due to normal fault only is as follows: 25 ms Specification -3 ms GFI turn-on time (15k and 1F) -8 ms Potential loss of one half-cycle due to fault current sense of half-cycles only -4 ms Time required to open a sluggish circuit breaker 10 ms Maximum integration time that could be allowed 8 ms Value of integration time that accommodates component tolerances and other variables
Ct=
1x T V
(5)
Where T=integration time V=threshold voltage I=average fault current into Ct
I=
120VAC(rms) RB heavy fault current generated (swamps ITH)
1 turn 1000 turns current division of input sense transformer
x
RN RG + RN portion of fault current shunted around GFI
x
x
1 2
x
0.91 rms to average conversion
(6)
Ct charging on halfcycles only
therefore:
Ct =
120 500
0.4 x 1.6+0.4 x
1 1000 17.5
x
1 2
x
0.91
x 0.0008 (7)
Ct = 0.01F
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UTC LM1851
APPLICATION CIRCUITS
LINEAR INTEGRATED CIRCUIT
In practice, the actual value of C1 will have to be modified to include the effects of the neutral loop upon the net charging current. The effect of neutral loop induced currents is difficult to quartile, but typically they sum with normal fault currents, thus allowing a larger value of C1. For UL943 requirements, 0.015F has been found to be the best compromise between timing and noise. For those GFI standards not requiring grounded neutral detection, a still larger value capacitor can be used and better noise immunity obtained. The larger capacitor can be accommodated because RN and RG are not present, allowing the full fault current, I, to enter the GFI. In Figure 2, grounded neutral detection is accomplished by feeding the neutral coil with 120 Hz energy continuously and allowing some of the energy to couple into the sense transformer during conditions of neutral fault.
TYPICAL APPLICATION
GND/NEUTRAL COIL SENSE COIL
HOT LOAD NEUTRAL
MOV 200:1 1000:1
LINE
CIRCUIT BREAKER
HIGH COIL 0.01/400V 10 F + TANT
15K/2W
SCR
7 TIMING CAP 1 SCR TRIGGER 5 OP AMP Ct OUTPUT 0.015 8 VCC RSET* + 1.0F TANT
-IN +IN RSET GND
2 3 6 4
0.0033
200 pF
0.01/400V
0.01
* Adjust RSET for desired sensitivity
FIGURE 2. 120Hz Neutral Transformer Approach
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UTC LM1851
DEFINITION OF TERMS
LINEAR INTEGRATED CIRCUIT
Normal Fault plus Grounded Neutral fault: The combination of the normal fault and the grounded neutral fault, as shown by the dashed lines.
Normal Fault An unintentional electrical path , R between B, the load terminal of the hot line and the ground, as shown by the dashed lines
HOT LINE
NEUTRAL RG GFI
HOT RLOAD RB NEUTRAL
HOT LINE
NEUTRAL GFI
HOT RLOAD
NEUTRAL RN RG RB
Grounded Neutral Fault: An unintentional electrical path between the load terminal of the neutral line and the ground, as shown by the dashed lines.
HOT LINE
NEUTRAL GFI
HOT RLDAD NEUTRAL
RN RG
UTC
UNISONIC TECHNOLOGIES CO., LTD.
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UTC LM1851
1000 Average Trip Time vs Fault Current CIRCUIT OF FIGURE 2
LINEAR INTEGRATED CIRCUIT
100 FAULT CURRENT ON LINE (mA(rms)) Normal Fault Current Threshold vs R SET
RSET= 7V If (rms)*x(0.91) SENSE TRANSF0RMER 1000:1
TYPICAL PERFORMANCE CHARACTERISTICS
FAULT CURRENT (mA)
100
UL943 NORMAL FAULT
10
10
0
0.01
0.1 1.0 TRIP TIME (SECONDS)
10
1 100k
1M RSET ()
Pin 1 Saturation Voltage vs External Load Current, IL
10M
OUTPUT DRIVE CURRENT@PIN 1 ( A)
1400 1200 1000 800 600 400 200 0
Output Drive Current vs Output Voltage
10 PIN 1 SATURATION VOLTAGE (V)
1 5mA 31V 8 IL 0.1 1mA 1
31V 8 5mA
1mA
1
A
VPIN1
V
0.01 0.1 4 100 1 10 EXTERNAL LOAD CURRENT, L (mA) I
4 0 5 10 15 25 20 30 OUTPUT VOLTAGE@ VPIN1 (V) 35
UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
UTC
UNISONIC TECHNOLOGIES CO., LTD.
9
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